1. Field of the Invention
This invention relates generally to the structure and fabrication process of power MOSFETs. More particularly, this invention relates to a novel, improved, and simplified process for fabricating a power MOSFET device at lower cost wherein heavily doped p.sup.+ regions buried underneath the n.sup.+ doped source regions are provided to reduce the body-to-source resistance R.sub.bs for preventing an incidental turning on of the parasitic NPN bipolar such that the device ruggedness is improved.
2. Description of the Prior Art
Manufacture of power MOSFET transistors still experiences the difficulties of product reliability and high fabrication costs. These difficulties are caused by a manufacture process for the purpose of increasing the device ruggedness. In order to achieve this goal, a more complicated process, involving the formation of spacer, is applied which employ oxide spacers to form the self aligned buried regions underneath the source regions with higher body-dopant concentration. In carrying out the processing steps to form these oxide spacers, a special anisotropic etching process, e.g., a reactive ion etching (RIE), process is performed which often leads to special problems and limitations in manufacturing the power device. Leakage of the junction currents, directly below the space edges is often reported in devices formed with oxide spacer. The problems can be attributed to silicon loss and spacer etch damages in the substrate which also lead to defects formed in the subsequent source implant and anneal. The performance of the power device and the reliability are therefore adversely affected due to these difficulties when spacers are implemented which are formed with these processing steps.
Various internal parasitic components often impose design and performance limitations on a conventional power metal oxide silicon field effect transistor (MOSFET) structure and processing steps of fabrication for manufacturing a MOSFET transistor. Among these parasitic components, special care must be taken in dealing with a parasitic npn bipolar junction transistor (BJT) formed between the source, the body, and the drain. Under static conditions the base and emitter of the parasitic BJT are shorted, leaving only the body-drain diode effective. However, under transient conditions and in avalanche breakdown, the parasitic BJT may be incidentally activated which can seriously degrade the overall performance of the MOSFET. Under the circumstances when the parasitic bipolar junction transistor is incidentally activated, snap back may occur which can cause permanent damages to the device. For this reason, precaution must be taken to increase the ruggedness of the device by taking into account that an incidental activation of the parasitic BJT should be prevented in an avalanche breakdown condition when large amount of hole current is generated in the core cell area.
In order to better understand the design issues related to device ruggedness encountered in the prior art, general descriptions for the structure of a conventional power MOSFET device and design issues relating to device ruggedness are first discussed. FIG. 1 shows a typical vertical double diffused MOS (VDMOS) device which uses a double diffusion technique to control the channel length 1. Two successive diffusions are performed with first a p diffusion using boron, then a n diffusion using either arsenic or phosphorus, to produce two closely spaced pn junctions at different depths below the silicon surface. With this pn junction, as shown in FIG. 1, the VDMOS supports the drain voltage vertically in the n.sup.- epilayer. The current flows laterally from the source through the channel, parallel to the surface of the silicon. The current flow then turns through a right angle to flow vertically down the drain epilayer to the substrate and to the drain contact. The p-type "body" region in which the channel is formed when a sufficient positive voltage is applied to the gate and the channel length can be controlled through the processing steps. Because of the relative doping concentrations in the diffused p-channel region and the n- layer, the depletion layer which supports V.sub.DS, a drain to source voltage, extends down into the epilayer rather than laterally into the channel. Under the circumstances of avanlanche breakdown, a hole current, i.e., I.sub.h as shown in FIG. 1, is generated to flow from the breakdown region to the source. A voltage drop, I.sub.h R.sub.b, is generated over the parasitic NPN bipolar junction transistor as the hole current I.sub.h is transmitted via the p-body region which has a p-body resistance R.sub.b. When this voltage drop across this parasitic bipolar junction transistor reaches a certain level, the parasitic bipolar transistor is turned on. Activation of the parasitic bipolar transistor, as discussed above, could cause snap-back and permanent damages to the MOSFET device.
For the purpose of improving the device ruggedness, Motorola discloses a HDTMOS-2 structure as that shown in FIG. 2 (please refer to Electronic Engineering Times, Apr. 8, 1996, Page 78). After n.sup.+ source impant, a dielectric layer is grown on top of the polysilicon gate. The dielectric layer is applied as a spacer for boron implant blocks, automatically self aligned with the source regions. This heavily doped p.sup.+ region underneath the source region can reduce the body to source resistance R.sub.b in the p-body region thus decreasing the voltage drop I.sub.h R.sub.b whereby the ruggedness of the MOSFET device is improved.
The difficulties arising from spacer implementation, such as the structure discussed above, can be better understood from a brief review of a typical spacer formation processes. In order to fabricate side-wall spacers on the edge of a poly gate, a conformal CVD oxide layer is deposited. A preferred method is to decompose TEOS at 725.degree. C. to form a layer with excellent conformality. The layer tends to have greater thickness along the vertical edges of poly gates then on the flat areas. An anisotropic etch process will remove the oxide in the flat areas while leaving the spacers at the side walls of the poly gates. In order to account for variations in the spacer oxide layer thickness, some over etch is necessary. During the over-etch time, the field oxide and the silicon in the source or body junction regions may also be etched. Which may lead to the problems and difficulties discussed above. Furthermore, the uniformity of the RIE process is difficult to control and the slope of the spacer may vary along the side-walls of the poly gates. Which may then affect the self alignment and dopant profiles in subsequent ion implant operations to form the buried body-regions and the source regions. These difficulties in applying the RIE process cannot be easily resolved when the spacers are employed.
In a paper published by Laska et al. entitled "A Low Loss/Highly Rugged IGBT-Generation-Based on a Self Aligned Process with Double Implanted N/N+ Emitter" (Proc. of the 6th Internat. Symposium on Power Semiconductor Device & IC's, Davos, Switzerland May 31-Jun. 2, 1994, PP 171-172), a new V-IGBT chip is disclosed. In order to realize a cell design for low on-state voltage in combination with high ruggedness, special cell structure is implemented. The cell structure is manufactured by applying the steps that after an isotropic etching of the polysilicon gate and after the p-well diffusion a first implant is carried out with one special part, e.g., n-implant, of the total emitter dose. Then an oxide spacer of a width of approximately 0.5 .mu.m is produced. Using this oxide spacer, a self aligned implant of the highly doped p.sup.+ well extremely close to the beginning of the channel is carried out. Then the second emitter implant, e.g., n-implant, follows using the same oxide spacer. Thus the emitter is formed with a double implant. In the critical area near the source contact, without the p.sup.+ doping, the parasitic emitter efficiency is adjusted by a low implant dose. Inside the less critical area in the body, the high dose is present which is necessary for the ohmic-Si/metal contact where the parasitic emitter efficiency is reduced by the p.sup.+ well. Laska et al. disclose a structure and fabrication method to increase device ruggedness by the use of oxide spacer as that shown in FIG. 3. Such fabrication processes require more processing steps. The product reliability may be adversely affected by the more complicated fabrication processes and the costs of device production are also increased due to the requirement of applying the spacer.
In order to reduce the body to source resistance, Korman et al. disclosed in U.S. Pat. No. 5,119,153 entitled "Small Cell Low Contact Resistance Rugged Power Field Effect Devices and Method of Fabrication" (issued on Jun. 2, 1992), a power field effect semiconductor device wherein an oxide or nitride spacer is used to form a heavily doped portion of a body region which is self aligned with respect to an aperture in the gate electrode. In forming the spacer, the nitride or oxide layer has to be formed and then anisotropically etched by reactive ion etching (RIE) in order to form the space along the side wall of the poly silicon gate. Therefore, the device disclosed by Korman et al. is faced with the same technical difficulties associated with an-isotropic etching, such as an RIE process, as discussed above. Difficulties in manufacturability arising from imprecision of process control in applying this RIE method may also cause the cost of production to increase.
Therefore, there is still a need in the art of power device fabrication, particularly for power MOSFET design and fabrication, to provide a simplified and improved fabrication process that would resolve these limitations.